1. Field of the Invention
The present invention relates to data transmission, and more particularly to serializing and sending, bit by bit, a data word and a bit clock with an embedded data word boundary.
2. Background Information
FIG. 1 illustrates a known serializer in a block schematic form. A parallel data word 10 is loaded into a buffer register 12 with a word clock 14. The word clock 14 is also fed to a phase locked loop (PLL) or a delay locked loop (DLL) 16, hereinafter PLL will be used to refer to both the PLL and DLL. The PLL generates a bit clock 18 that loads the shift register 20 and subsequently shifts out the data in the shift register 20 serially bit by bit through a cable or transmission line driver 22. The bit clock 18 that shifts the data out bit by bit stays synchronized to the bit positions within the word by the PLL. Along with the serial bits from driver 22, a word clock 24 is output via driver 26. The receiver will be able to distinguish the beginning and ending of the serial data stream by referencing the bit stream via the word clock.
FIG. 2 shows a receiver circuit that de-serializes the bits to form words. The serial data 30 is input to a shift register 32. The word clock 34 is input to a PLL 36 that generates a bit clock 38 that is synchronized to the bit location in a word by the PLL. With this synchronization, the bit clock 38 properly loads the bit stream into the shift register 32. When the word has been received by the shift register 32 (as determined from the word clock), the PLL outputs a clock 40 that loads the parallel data in the shift register 32 into a buffer register 42. The word data 44 is in parallel form ready for use in the receiving system.
FIGS. 1 and 2 contain a buffer register that holds the word to be sent or the word just received. The buffer allows nearly the entire time for a word to be sent or received before the next word is loaded. The logic and the timing to accomplish these tasks are well known. However, the buffer registers are not required, and if not used, then the word to be sent and the word received must be loaded during a bit time. Again, such designs are well known in the art.
FIG. 3 shows a complete bidirectional system using the serializers as in FIG. 1 and de-serializers as in FIG. 2. Note that there are eight data lines and a single clock into each serializer and out from each de-serializer. The data and clock lines between the serializer and the de-serializer are typically differential signals each using two conductors.
The serializer/de-serializers of FIG. 3 each contain a PLL that are common in such devices. But, PLL's consume significant power, are complex, require long locking times, and occupy considerable chip real estate. It would be advantageous to dispense with PLL's.
FIG. 4 shows a generic timing chart that illustrates the serial sending of a data word. A word clock 60 is fed to a PLL that generates a synchronous bit clock 62, the word clock 60 must occur often enough for the PLL to remain locked. The data bits are loaded into a shift register using a word clock edge. Then, the data bits in the shift register are shifted out serially by the bit clock 62. In FIG. 4 an eight bit word is shifted out on the rising edge of the bit clock 62.
A similar operation applies to the receiving of the serial data. In FIG. 2, a word clock 34 is received and applied to a PLL 36 that generates a synchronous (to the word clock) bit clock that is used to load the data bits into a receiving shift register. Data bits must be stable when the clocks cause the data bits to be sent and to be received. Time delays are designed into such systems to accomplish this, as known in the art. In the case shown, the data bits are sent out synchronously where the first bit of the next word is sent out directly after the last bit of the prior word. In other instances the data may be sent out asynchronously, typically using a start and stop bit that frames the data bits. In both the synchronous and asynchronous cases, system means must be employed, as are well known in the art, to prepare the sender and the receiver to properly send and receive the data. Also, systems are arranged to send data, then, after sending, to receive data; while other systems can send and receive simultaneously. The former is referred to as half duplex and the latter as duplex. Again, system designers understand the limitations and requirements of such systems to properly send and receive data.
It is axiomatic that the receiving system must be able to distinguish data bits and word boundaries from a stream of serial bits, as discussed above. U.S. Pat. No. 4,841,549 to Knapp sends serial data with a bit clock. In this application, the bit clock, traveling with the data bits, is received by a re-triggerable; a one-shot. When a word boundary is created by the sender, a bit clock is not sent. The receiver one-shot times out and the ensuing missing bit clock is interpreted as a word boundary. In this case, the re-triggerable one-shot must be carefully set to receive the bit clocks in order to trigger and to time out properly. This approach is limited by requiring an accurate one-shot set up and then the use of a set bit clock that cannot change. The present invention employs a different approach and circuit compared to the Knapp patent, and the present invention is not so limited in its applications.
In general, transferring serial data offers an advantage that the cable running between the sending and receiving systems need only have a few signals (if differential signals, one data pair and one clock pair) carrying wires (and, of course, if not differential, a common return wire could be used). In contrast, sending data over cables in parallel requires line drivers for each bit in a word and, at least, a clock driver. These parallel drivers consume high power and output high currents that create significant system noise.
In applications where cables or transmission lines are not used, but where parallel data is sent between integrated circuit packages, many pins on those packages must be set aside for each bit of the parallel data. In the newer designs, using sixty-four and one hundred and twenty-eight bits, the pins available on the packages become a design limitation. Larger packages and ball grid array and similar packages that provide pins over the entire bottom surface of a package address this problem. However, the problem persists. Applications that may suffer from these limitations include virtually all computing systems with complex displays, e.g. cell phones, desk-top and lap top computers, electronic games, computing systems with off-chip memory, any computing system addressing bulk memory, and electronic instrumentation, monitoring and controlling equipment.
Up to the present time, serializing and de-serializing data entails using PLL's that are complex and costly of power chip space and time, as discussed above. Serializing and de-serializing would find greater acceptance if these limitations were removed.